Time-to-digital converters (TDCs) are increasingly popular in many applications including time of flight measurements, phase detectors in phase-locked-loops (PLLs), data converters, high speed signal capturing, demodulators, and other measurement or instrumentation applications. For example, TDCs have been implemented in pulsed time-of-flight laser radars used in traffic speed cameras, millimeter-precision object detection and localization, anti-collision radars and proximity sensors, and so forth. These applications typically require a precise single-shot measurement within a high dynamic range.
With the downscaling of the minimal feature size of modern submicron CMOS technologies, TDCs are very useful in other applications as well. This is the case when it is profitable to replace badly scaling analog circuits with TDCs. Since technology scaling implies voltage scaling while noise does not scale along, variability becomes more important. This requires more effort to be put into analog circuits, which leads to increased power consumption. Digital speed however does scale with technology. The robustness of digital circuits is much more preserved, although it is also compromised with variability. However, since TDCs directly profit from enhanced speed performance, switching from the analog to the digital time domain can significantly reduce the power consumption for equal performance, especially for designs in sub-100 nm technology nodes.
In this context, an alternative scheme for an Analog to Digital Converter (ADC) has been to use an Asynchronous Delta-Sigma Modulator (ADSM) in combination with a high precision TDC. The ADSM converts the analog input u(t) to a duty cycle modulated square wave y(t) with a limit cycle frequency flc offlc=(π/2h)fint with the hysteresis value h of the comparator and the unit-gain frequency fint of the integrator. The time information of the square wave is measured with the TDC which returns a digital value m[k]. Finally a digital demodulation algorithm is used to demodulate the square wave back to the original input signal, but now in the digital form z[k].
The in-band noise can further be reduced by placing the ADSM, TDC and demodulator in an n-th order delta-sigma loop that shapes the quantization noise of the TDC to higher frequencies.
The main drawback of a multi-bit feedback loop is the need of a high-precision Digital to Analog Converter (DAC), which must have the same linearity requirements as the whole converter. This is increasingly difficult to achieve with higher numbers of bits in the TDC output, which makes the DAC a very expensive component in terms of area and power consumption.